Balloon hardware overview
The Balloon 3 design process started in 2004, when the PXA270 was chosen as a logical upgrade from the SA1110. Various meetings were held to refine practical aspects of the design like which connectors to use, how to group signals to connectors, and also how to map the pxa270 functionality onto the existing expansion bus, given a multitude of new functions and signals. In the light of unreliablity problems with connectors used on balloon2, due to the weakness of the little pre-crimped leads you get to put in them, Balloon 3 uses FPC/FFC connectors throughout, which allows more IO in the same space. It also has a built-in 8/16-bit bus (Samosa) for driving any simple devices you might need (IO, displays, logging equipment), and the programmable logic has been much enhanced. You can now have either a CPLD version like Balloon 2, but with more uncommitted logic as much less glue logic is needed external to the CPU, or an FPGA so that it is possible to do fancy DSP-type functionality on-board.
The information below is for the 'E1' build of balloon which is the initial engineering build, before doing 'design-for-manufacture' work. Some of the files still refer to P1/P2 build vintage at the moment - check the info is correct before desiging anything. There will be one more iteration for main productions runs. Any design changes resulting from debugging could have an impact on the placement of parts.
All supplied as PDF files.
Version 0.21 Schematic and Layout files
Showing schematics, components and netlist, and board layer layouts.
Datasheets for the chips
Not available yet
Clickable board images
Top of v3.21 'E1' build board - FPGA variant
Bottom of v3.21 'E1' build board