Author: wookey
Date: 2010-03-19 14:43:20 +0000 (Fri, 19 Mar 2010)
New Revision: 1024

Modified:
   balloon/branches/novlio/bootldr/boot-pxa.s
   balloon/trunk/bootldr/boot-pxa.s
Log:
Clarify MCS2_INIT register settings for VLIO/noVLIO
in comments. Making novlio branch and HEAD match.



Modified: balloon/branches/novlio/bootldr/boot-pxa.s
===================================================================
--- balloon/branches/novlio/bootldr/boot-pxa.s	2010-03-11 18:57:16 UTC (rev 1023)
+++ balloon/branches/novlio/bootldr/boot-pxa.s	2010-03-19 14:43:20 UTC (rev 1024)
@@ -2623,7 +2623,15 @@
 #if defined(CONFIG_MACH_BALLOON)
 // configure nCS4 as VLIO
 MSC2_INIT:
-// this is the value for VLIO - fast timings to be slowed by wait states inserted by the CPLD
+// this register controls VLIO/No VLIO (which must match VHDL)
+// and is affected by KERNEL CPU_FREQ option
+// Register layout:
+// 15  14 13 12 11 10 09 08 07 06 05 04 03  02 01 00
+//RBUF|  RRR   |    RDN    |    RDF    |RBW|   RT
+
+// VLIO (variable latency IO) is off by default as it causes suspend failure
+// on some hardware if USB devices are plugged in - appears to be pxa bug
+// VLIO has fast timings to be slowed by wait states inserted by the CPLD
 // assume 104MHz memory clock because we can't get the timings we need for
 // Samosa at 208MHz. Note kernel patch (balloon3-cpufreq) which sets memory
 // clock to 104MHz at all CPU clock frequencies.
@@ -2634,6 +2642,7 @@
 // RDF is minimum number of clock cycles nOE/nPWE are asserted
 // we want this to be 3 for quick NAND access
 // any slower cycles will be created by the VLIO timer in CPLD
+// RDF=3, RDN=7, RRR=6, RBUF=1, RBW=0, RT=4
 //.long 0x74a47734
 // 15  14 13 12 11 10 09 08 07 06 05 04 03  02 01 00
 //RBUF|  RRR   |    RDN    |    RDF    |RBW|   RT
@@ -2641,6 +2650,10 @@
 // SRAM timing
 // RDF=14, RDN=14, RRR=4, RBUF=0, RBW=0, RT=1
 .long 0x74a44ee1
+//below is magic value for use with 'fast bus' mode - i.e if
+//CPU_FREQ turned on in kernel
+// RDF=13, RDN=13, RRR=5, RBUF=0, RBW=0, RT=1
+//	.long 0x74a45dd1
 #else
 MSC2_INIT:
 	.long 0x74a42494

Modified: balloon/trunk/bootldr/boot-pxa.s
===================================================================
--- balloon/trunk/bootldr/boot-pxa.s	2010-03-11 18:57:16 UTC (rev 1023)
+++ balloon/trunk/bootldr/boot-pxa.s	2010-03-19 14:43:20 UTC (rev 1024)
@@ -2623,7 +2623,15 @@
 #if defined(CONFIG_MACH_BALLOON)
 // configure nCS4 as VLIO
 MSC2_INIT:
-// this is the value for VLIO - fast timings to be slowed by wait states inserted by the CPLD
+// this register controls VLIO/No VLIO (which must match VHDL)
+// and is affected by KERNEL CPU_FREQ option
+// Register layout:
+// 15  14 13 12 11 10 09 08 07 06 05 04 03  02 01 00
+//RBUF|  RRR   |    RDN    |    RDF    |RBW|   RT
+
+// VLIO (variable latency IO) is off by default as it causes suspend failure
+// on some hardware if USB devices are plugged in - appears to be pxa bug
+// VLIO has fast timings to be slowed by wait states inserted by the CPLD
 // assume 104MHz memory clock because we can't get the timings we need for
 // Samosa at 208MHz. Note kernel patch (balloon3-cpufreq) which sets memory
 // clock to 104MHz at all CPU clock frequencies.
@@ -2634,9 +2642,17 @@
 // RDF is minimum number of clock cycles nOE/nPWE are asserted
 // we want this to be 3 for quick NAND access
 // any slower cycles will be created by the VLIO timer in CPLD
+// RDF=3, RDN=7, RRR=6, RBUF=1, RBW=0, RT=4
 .long 0x74a47734
-//below is correct magic value for use with 'fast bus' mode - i.e if
+// 15  14 13 12 11 10 09 08 07 06 05 04 03  02 01 00
+//RBUF|  RRR   |    RDN    |    RDF    |RBW|   RT
+// for Samosa, asssuming 104MHz bus clock,
+// SRAM timing
+// RDF=14, RDN=14, RRR=4, RBUF=0, RBW=0, RT=1
+//.long 0x74a44ee1
+//below is magic value for use with 'fast bus' mode - i.e if
 //CPU_FREQ turned on in kernel
+// RDF=13, RDN=13, RRR=5, RBUF=0, RBW=0, RT=1
 //	.long 0x74a45dd1
 #else
 MSC2_INIT: