Author: wookey
Date: 2010-03-19 17:20:37 +0000 (Fri, 19 Mar 2010)
New Revision: 1025
Added:
balloon/trunk/patches/
balloon/trunk/patches/README
balloon/trunk/patches/tcl-pinko-serial.patch
balloon/trunk/patches/vlio-bootldr.patch
balloon/trunk/patches/vlio-vhdl.patch
Log:
Add new patches dir as a place to collect useful non-kernel patches
Added: balloon/trunk/patches/README
===================================================================
--- balloon/trunk/patches/README (rev 0)
+++ balloon/trunk/patches/README 2010-03-19 17:20:37 UTC (rev 1025)
@@ -0,0 +1,13 @@
+This dir contains useful patches for things that are not part of the
+normal base release.
+
+Currently we have:
+
+1) the VLIO patches for bootldr and vhdl. You need both
+of these or it won't work at all! Change the VHDL first, not the
+bootloader when uploading binaries, otherwise you can brick your
+balloonboard to a 'needs JTAG' state.
+
+2) The TCL serial logic patch which patches Com1 serial through to the
+pinko connector instead of the normal one. This logic is incompatible
+with other hardware so can not be in by default.
Added: balloon/trunk/patches/tcl-pinko-serial.patch
===================================================================
--- balloon/trunk/patches/tcl-pinko-serial.patch (rev 0)
+++ balloon/trunk/patches/tcl-pinko-serial.patch 2010-03-19 17:20:37 UTC (rev 1025)
@@ -0,0 +1,24 @@
+--- trunk/vhdl/fpga/balloon3.vhd
++++ branches/novlio/vhdl/fpga/expected.wiggle
+@@ -743,15 +743,15 @@
+
+ -- On tcl board com1 goes on to pinko
+ -- connect pinko wiring up. CTS is bit 2 of general control register.
+---pinko_txd <= com1_bttxd;
+---com1_btrxd <= pinko_rxd;
+---pinko_cts <= control_latch(2);
++pinko_txd <= com1_bttxd;
++com1_btrxd <= pinko_rxd;
++pinko_cts <= control_latch(2);
+
+ -- On other boards com1 is not copied to pinko
+-pinko_txd <= '0';
+-pinko_cts <= '1';
++--pinko_txd <= '0';
++--pinko_cts <= '1';
+ ---- allow external devices to talk to COM1
+-com1_btrxd <= 'Z';
++--com1_btrxd <= 'Z';
+
+ --DEBUG
+ --green_led <= nand_select;
Added: balloon/trunk/patches/vlio-bootldr.patch
===================================================================
--- balloon/trunk/patches/vlio-bootldr.patch (rev 0)
+++ balloon/trunk/patches/vlio-bootldr.patch 2010-03-19 17:20:37 UTC (rev 1025)
@@ -0,0 +1,16 @@
+--- branches/novlio/bootldr/boot-pxa.s
++++ trunk/bootldr/boot-pxa.s
+@@ -2644,11 +2644,11 @@
+ // any slower cycles will be created by the VLIO timer in CPLD
+ // VLIO:
+ // RDF=3, RDN=7, RRR=6, RBUF=1, RBW=0, RT=4
+-//.long 0x74a47734
++.long 0x74a47734
+ // No VLIO:
+ // SRAM timing for Samosa, asssuming 104MHz bus clock
+ // RDF=14, RDN=14, RRR=4, RBUF=0, RBW=0, RT=1
+-.long 0x74a44ee1
++//.long 0x74a44ee1
+ //below is magic value for use with 'fast bus' mode - i.e if
+ //CPU_FREQ turned on in kernel
+ // RDF=13, RDN=13, RRR=5, RBUF=0, RBW=0, RT=1
Added: balloon/trunk/patches/vlio-vhdl.patch
===================================================================
--- balloon/trunk/patches/vlio-vhdl.patch (rev 0)
+++ balloon/trunk/patches/vlio-vhdl.patch 2010-03-19 17:20:37 UTC (rev 1025)
@@ -0,0 +1,57 @@
+--- trunk/vhdl/fpga/balloon3.vhd
++++ branches/novlio/vhdl/fpga/expected.wiggle
+@@ -434,7 +434,7 @@
+ Port Map(
+ data_bus_in => cpu_data(15 downto 0),
+ data_bus_out => nand_data_out,
+- cpu_nwe => cf_npwe,
++ cpu_nwe => cpu_nwe,
+ cpu_noe => cpu_noe,
+ cpu_rdnwr => cpu_rdnwr,
+ internal_RnS => internal_RnS,
+@@ -508,7 +508,7 @@
+ -- data_bus_in => debug_data,
+ data_bus_out => samosa_data_out,
+ reg_add => cpu_a(4 downto 2),
+- cpu_nwe => cf_npwe,
++ cpu_nwe => cpu_nwe,
+ cpu_noe => cpu_noe,
+ cpu_rdnwr => cpu_rdnwr,
+ samosa_select => samosa_select,
+@@ -558,7 +558,7 @@
+ RESET_STATE => CF_reset_state,
+ D => cpu_data(7 downto 0),
+ register_select => cf_control_select,
+- nWE => cf_npwe,
++ nWE => cpu_nwe,
+ EN => '1',
+ RnS => internal_RnS,
+ Q => cf_control,
+@@ -571,7 +571,7 @@
+ RESET_STATE => cpu_Control_reset_state,
+ D => cpu_data(7 downto 0),
+ register_select => general_control_select,
+- nWE => cf_npwe,
++ nWE => cpu_nwe,
+ EN => '1',
+ RnS => internal_RnS,
+ Q => control_latch,
+@@ -584,7 +584,7 @@
+ RESET_STATE => X"00",
+ D => cpu_data(7 downto 0),
+ register_select => interupt_control_select,
+- nWE => cf_npwe,
++ nWE => cpu_nwe,
+ EN => '1',
+ RnS => internal_RnS,
+ Q => interupt_control,
+@@ -614,7 +614,8 @@
+ -- and when all IO is not parked. This is because the 48MHz clock
+ -- stops at standby/shutdown and VLIO operations can hang then.
+ vlio_disable <= '1' when samosa_park='1' and nand_park='1' else '0';
+-cpu_rdy <= vlio_rdy when cpu_ncs4 = '0' and vlio_disable = '0' else '1';
++-- cpu_rdy <= vlio_rdy when cpu_ncs4 = '0' and vlio_disable = '0' else '1';
++cpu_rdy <= '1';
+ --vlio_nstart <= '0' when cpu_ncs4 = '0' and (cpu_noe = '0' or cf_npwe ='0') else '1';
+ vlio_nstart <= '0' when cpu_ncs4 = '0' else '1';
+ -- choose the delay
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